apexchipset.com — AI EDA Web IDE

📁 RTL Files

📄 main.sv

📁 Results

📊 Metrics

🔌 Netlist View

⚠️ DRC Results

📁 Logs

📝 Flow Logs

Area (µm²)

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Setup Slack (ns)

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Power (mW)

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Cell Count

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DRC Violations

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Wirelength (µm)

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Netlist visualization will appear here after synthesis.

DRC results will appear here after routing.

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