🚀 Getting Started
APEX-EDA is the first cloud-native, AI-powered EDA platform. It takes you from RTL code to tapeout-ready GDSII entirely in your browser. No licence servers, no complex toolchains, no $100K annual seat fees.
1 Create Account & Web IDE
- Go to apexchipset.com/register
- Choose Startup ($199/mo, individual) or Enterprise (custom)
- Enter email, name, password, verify email
- Login — land directly in the APEX Web IDE
No installation needed
Everything runs in your browser. No downloads, no license dongles, no $100K startup fees.
Web IDE Layout
Left: File Browser | Center: Monaco Code Editor | Right: Tool Launcher | Bottom: Results Panel. Keyboard: Enter = Synthesis, Shift+Enter = Full Flow, L = Lint
2 Your First Design — 8-bit Counter
Step 1: Write RTL
Replace default code:
module counter (
input wire clk, rst_n,
output reg [7:0] count
);
always @(posedge clk or negedge rst_n)
if(!rst_n) count <= 8'd0; else count <= count + 1'b1;
endmodule
Step 2:
Press L — Lint (syntax check)
Step 3:
Press Enter — Synthesis (RTL → gates)
Step 4:
Click Simulate → Run — Verilator simulation with auto-generated testbench
Step 5:
Click Schematic — view circuit diagram
What's next?
Try AI Optimisation, Physical Design (Floorplan → PnR → Clock Tree), and the X1 Tapeout Flow. Each is one click.
📐 Design Flow Overview
Industry-proven stages with AI acceleration at every step:
Full pipeline: One click on Run Flow or Shift+Enter executes RTL→Synthesis→Floorplan→PnR→CTS→DRC/LVS→GDSII automatically.
📝 RTL Editor
Monaco-based (VS Code engine). Verilog (1364-2001), SystemVerilog (1800-2012), VHDL (1076). Syntax highlighting, multi-cursor, bracket matching.
📂 File Management
Create new modules, upload .v/.sv/.vhd. Multi-file support. Auto-save. Top-level detection automatic.
📎 SDC Constraints
Clock frequency, I/O delays, false paths, generated clocks. Inline editor.
🏷️ Netlist Viewer
Gate-level netlist post-synthesis: cell types, pin connections, hierarchy.
🔬 Hierarchy Explorer
Module hierarchy navigation. Collapse/expand submodules. Cross-probe to RTL.
📊 RTL Metrics Dashboard
Lines, module depth, port widths, comb/seq ratio, FSM count, inferred memory.
🔄 SDF Back-Annotation
Post-layout SDF annotation into simulation for signoff-accurate timing.
🔧 Synthesis Tools
🔧 Core Logic Synthesis Yosys-based engine with APEX optimisation passes. Compiles RTL → gate-level netlist. Output: cell area, estimated power, top-20 critical paths.
POST /api/design/{id}/run-synthesis
🔄 Retiming Auto-moves FFs across combinational logic. 15-30% frequency improvement on poorly pipelined designs.
POST /api/design/{id}/retiming
⚡ Clock Gating Auto-inserts clock gating. 20-40% dynamic power reduction.
POST /api/design/{id}/clock-gating
🎯 PDK Mapping Map netlist to foundry PDK: SkyWater 130nm, GF 180nm, TSMC 28nm/16nm, IHP 130nm.
POST /api/design/{id}/pdk-map
🔬 FSM Extraction Extract visual state machine diagram from RTL — states, transitions, encoding.
POST /api/design/{id}/fsm-extract
🔷 Area Report Die area breakdown: sequential, combinational, IO, macros, memories.
GET /api/design/{id}/area
💡 Constraint Check Validate SDC — missing clocks, waveform errors, unconstrained paths.
POST /api/design/{id}/constraints/check
📦 Snapshots Point-in-time design snapshots. Restore or diff between any two snapshots.
POST /api/design/{id}/snapshot
🔀 Fork Design Branch a copy for what-if analysis. Independent synthesis/PnR flows.
POST /api/design/{id}/fork
⏱ Timing & Analysis
⏱ Static Timing Analysis (STA) Full-chip STA. Setup/hold slacks across all paths. WNS, TNS reported.
POST /api/design/{id}/sta
📈 Critical Paths Top-20 Source FF, dest FF, combinational delay, net RC, clock skew, slack.
GET /api/design/{id}/critical-paths
🎭 Multi-Corner Timing PVT corners: SS (worst), TT (typical), FF (best). Full report per corner.
POST /api/design/{id}/multicorner-timing
🔌 Power Analysis Dynamic + static power. Breakdown: clock, seq, comb, IO. Activity-factor driven.
POST /api/design/{id}/pwr-analysis
⚡ IR Drop (AI) ML model predicts PDN voltage drop. Flags timing-critical hotspots.
POST /api/design/{id}/ai/ir-drop
🔀 Crosstalk Analysis Coupled nets, glitch propagation, aggressor-victim pairs.
POST /api/design/{id}/crosstalk
📐 Utilisation Report Core util %, cell density, whitespace analysis.
GET /api/design/{id}/utilisation
⚠️ CDC Analysis Clock Domain Crossing verification. Missing synchronisers, metastability risk.
POST /api/design/{id}/cdc
🔍 Signal Integrity Glitch analysis, noise margin, electromigration, wire self-heat.
POST /api/design/{id}/signal-integrity
🗺️ Congestion Map Routability heatmap with routing hotspot identification.
POST /api/design/{id}/congestion
📋 ECO Targeted netlist changes post-synthesis. No full re-synthesis needed.
POST /api/design/{id}/eco
🔧 Buffer Insertion Auto-fix max-cap/trans violations. Setup-time repair on long nets.
POST /api/design/{id}/buffer-insert
🌬️ Fanout Fix Replicate high-fanout nets to meet slew targets.
POST /api/design/{id}/fanout-fix
🔎 Antenna Check Gate-antenna violation check. Auto-inserts antenna diodes.
POST /api/design/{id}/antenna
🔍 Verification
Simulation
▶️ RTL Simulation Verilator-based. Auto-generates testbench. Outputs VCD waveforms.
POST /api/design/{id}/simulate
📊 Coverage Toggle, line, FSM, branch coverage.
POST /api/design/{id}/coverage
📝 Auto Testbench Gen Analyses ports → generates SystemVerilog testbench with directed+random tests.
POST /api/design/{id}/testbench-gen
Lint
🛠️ RTL Lint Syntax, width mismatch, inferred latches, comb loops, unconnected ports.
POST /api/design/{id}/lint
Formal
✅ Formal Equivalence SAT-based formal check: RTL ≡ post-synthesis netlist.
POST /api/design/{id}/formal
DRC / LVS / ERC
🔎 DRC Check Design Rule Check. Foundry-specific decks. Min spacing, width, enclosure, density.
POST /api/design/{id}/drc-check
🔄 LVS Layout vs Schematic: connectivity, device params, instance matching.
POST /api/design/{id}/lvs
📋 ERC Electrical Rule Check: floating nodes, power domain crossings, level shifters.
POST /api/design/{id}/erc
DFT (Design for Test)
🧪 ATPG Automatic Test Pattern Generation. Stuck-at fault model. Reports fault coverage % and top undetected faults.
POST /api/design/{id}/atpg
🔗 Scan Chain Insertion Auto-inserts scan chains. Configurable chain count, test clock, scan-enable.
POST /api/design/{id}/scan-chain
🏗 Physical Design
Floorplanning
🗺️ Floorplan Die size estimation, aspect ratio, IO pad ring, macro placement, power stripe planning.
POST /api/design/{id}/floorplan
🔋 Power Grid Power delivery network synthesis: stripe width, pitch, VDD/VSS mesh, EM checking.
POST /api/design/{id}/power-grid
Place & Route
🏭 OpenROAD PnR Full automated PnR via OpenROAD. Global placement, detailed placement, NDR routing.
POST /api/design/{id}/pnr
💡 AI Placement (GNN) HeteroGNN-based placement. ~12% better wirelength vs analytical placement.
POST /api/design/{id}/ai/place
🔀 AI Routing (RL) Reinforcement learning router. Optimises DRC-clean routing with minimal via count.
POST /api/design/{id}/ai/routing
Clock Tree Synthesis
🕐 Clock Tree H-tree + DME clock tree synthesis. Reports skew, insertion delay, total clock power.
POST /api/design/{id}/clock-tree
Advanced Physical
🛌 MTCMOS Multi-threshold CMOS power-gating insertion. Retention flops, power switch cells, always-on logic.
POST /api/design/{id}/mtcmos
🏭 GDS Preview Browser-based GDSII viewer. Pan, zoom, layer toggle, measurement.
GET /api/design/{id}/gds-preview
⚡ Bus Interface Gen Interface planner: AXI/AHB/APB bus width, clock crossing, pipeline depth.
POST /api/design/{id}/bus-interface
🤖 AI Tools
APEX-EDA features 6 specialised AI models covering the entire EDA flow:
🧠 GNN4LS Synthesis Graph Neural Network for Logic Synthesis. Learns optimal technology mapping from prior tapeouts. ~8% area reduction vs commercial tools.
POST /api/design/{id}/ai/gnn4ls
🤖 AI PPA Optimiser Multi-objective optimisation (Power, Performance, Area) using reinforcement learning. Pareto-optimal trade-off exploration.
POST /api/design/{id}/ai/ppa-optimize
💎 Crown Jewel AI Access the GLM-5.1 229B parameter model (Crown Jewel). EDA expert: analyze timing, suggest fixes, explain results. Ask questions in plain English.
POST /api/ai/crown-jewel
🔒 Atavus Air-Gapped AI On-premise AI engine. No data ever leaves your infrastructure. Design review, security audit, optimisation suggestions.
POST /api/ai/atavus-airgap
🤖 Autonomous EDA Agent Set a design goal in plain English (e.g. 'Synthesize a RISC-V core at 500MHz'). The agent plans and executes the entire flow autonomously.
POST /api/design/{id}/ai/run-agent
📊 AI Timing Optimiser GNN-based timing prediction. Identifies fixable violations before PnR. Recommends cell sizing and threshold voltage swaps.
POST /api/design/{id}/ai/timing
🔍 Similar Designs AI search across all designs. Recommends floorplan macros, timing constraints, and testbench patterns from similar past projects.
POST /api/design/{id}/ai/similar-designs
🔧 AI DRC Fix Auto-generates DRC fix patches from violation heatmap. AI learns from previously fixed violations.
POST /api/design/{id}/ai/drc-fix
📚 Library Management
Standard cell libraries for multiple foundries and technology nodes.
📚 Library Profiles Browse and compare cell libraries across PDKs: drive strengths, threshold voltages, area, timing.
GET /api/library/profiles
🔬 Library Cells Query cell library: cell type, drive strength, Vt flavour, area, pin capacitance, timing arcs.
GET /api/library/cells
🎯 Library Select Choose optimal PDK for your design. Auto-selects based on target frequency and gate count.
POST /api/library/select
📊 Library Report Full library characterisation report: cell count by type, timing corners, power numbers.
GET /api/library/report
🗺️ PDK Mapping Map generic cells to foundry-specific standard cells. Generates tech LEF file references.
POST /api/library/map
📋 Tech Library Technology-specific library data: metal stack, via layers, minimum pitch, DRC rule summary.
GET /api/tech-library
⚡ Generators
RISC-V Processor Generator
📟 RISC-V Generator Generates synthesizable RISC-V core RTL. Configurable: RV32I/RV64I, pipeline stages (3/5), branch predictor, cache, register file width.
POST /api/riscv/generate
Configuration options:
- ISA: rv32i, rv64i, rv32im, rv64im
- Pipeline: 3 or 5 stages
- Cache: up to 16KB I-cache + D-cache with configurable associativity
- Branch predictor: 2-bit saturating counter or gshare
- Output: Full synthesizable Verilog with top-level testbench
Natural Language → RTL Generator
💬 NL → RTL Describe your module in English, get synthesizable Verilog. Example: '8-bit counter with async reset and enable' generates correct RTL.
POST /api/nl/generate
Quantum Circuit Simulator
⚛️ Quantum Simulator Simulate quantum circuits: Hadamard, Pauli, CNOT, rotation gates. Configurable qubits (2-16), shots (up to 8192). Output: state vector, measurement distribution.
POST /api/quantum/simulate
Supported operations:
- Gates: H, X, Y, Z, Rx, Ry, Rz, CNOT, CZ, SWAP
- Measurement: single qubit, all qubits, partial collapse
- Analysis: state vector, Bloch sphere, entanglement entropy
Other Generators
📐 RTL Templates Pre-built module templates: FIFO, UART, SPI, I2C, AXI-lite, PWM, FSM patterns.
GET /api/templates
🧩 Bus Interface Gen AXI/AHB/APB bus planning: width, clock crossing, pipeline stages, ID width.
POST /api/design/{id}/bus-interface
🛒 IP Marketplace
Decentralised IP marketplace using LP (Loyalty Points) credits. Buy, sell, and license verified IP blocks.
🏪 Browse IP Library Browse available IP: RISC-V cores, crypto accelerators, peripheral controllers, PLL/DLL hard macros.
GET /api/ip-library
📦 IP Details View IP specifications, performance numbers, area, power. Download RTL (with valid purchase).
GET /api/ip-library/{ip_id}/rtl
💰 LP Balance Check your LP credit balance: available, held in escrow, total earned.
GET /api/marketplace/lp-balance
🛍️ Purchase IP Buy IP with LP credits. Supports perpetual and subscription licences. Escrow holds funds until delivery confirmed.
POST /api/marketplace/purchase
📋 My Purchases View purchase history, licences held, download links for acquired IP.
GET /api/marketplace/my-purchases
🏷️ My Listings List your own verified IP blocks for sale. Set price in LP credits.
GET /api/marketplace/my-listings
🏪 Vendor Storefronts Browse IP by vendor. See reputation scores, total sales, verified reviews.
GET /api/marketplace/vendors/{vendor}
📦 Download IP After purchase: download purchased IP RTL. Licence key watermarked per buyer.
GET /api/marketplace/download/{purchase_id}/{ip_id}
📦 Tapeout
X1 Tapeout Flow (Proven at 804K gates)
The APEX X1 is a complete tapeout-proven reference design (804K gates, SkyWater 130nm). Use the X1 flow as a template for your own tapeout.
🏭 X1 Tapeout Flow Full RTL-to-GDSII tapeout flow. Validates timing closure, DRC/LVS clean, GDSII generation. Proven tapeout at SkyWater 130nm.
POST /api/x1/tapeout
🔄 X1 Synthesis Optimised synthesis flow for the X1 reference. Includes clock gating, retiming, and PDK mapping.
GET /api/x1/synthesis
⚡ X1 Simulation Full chip simulation with auto-testbench. Validates all X1 blocks: SoC, memory controller, I/O subsystem.
POST /api/x1/simulate
✅ X1 Validation Pre-tapeout signoff checklist: timing, DRC, LVS, power, EM, IR drop. Generates signoff report.
POST /api/x1/validate
📊 X1 Status Check X1 tapeout status: flow stage, any violations, estimated completion.
GET /api/x1/status
💎 X2 Architecture Next-generation 7nm architecture. Performance model: 85 TOPS at 2.4 GHz, dual-core. Preview for advanced nodes.
GET /api/x2/architecture
📈 X2 Performance Model Compute performance projections: batch size, sparsity, model params, bandwidth. For AI accelerator design.
GET /api/x2/performance
🔌 X2 Power Estimation X2 estimated power at util% and activity factor. 7nm process values.
GET /api/x2/power
MPW Shuttles
🛰️ MPW Shuttles Multi-Project Wafer runs. View upcoming shuttle dates, costs per mm^2, available technologies. Book slot directly.
GET /api/mpw/shuttles
Tapeout Submission
📦 Tapeout Submit Submit your design for manufacturing. Includes: design name, gate count, technology, die size. System validates readiness and returns submission ID.
POST /api/tapeout/submit
🔐 Post-Quantum Tools
Integrated post-quantum cryptography tools and photonic interconnect simulation for next-gen chip designs.
🔑 Kyber-768 Keygen ML-KEM (CRYSTALS-Kyber) key generation. Generates public/private keypair.
POST /api/kyber-keygen
🔒 Kyber-768 Encaps Encapsulates shared secret using Kyber-768 public key. Ciphertext + shared secret.
POST /api/kyber-encaps
🔓 Kyber-768 Decaps Decapsulates ciphertext using Kyber-768 private key.
POST /api/kyber-decaps
💡 Photonic Link Training Simulates optical interconnect link training: bias tuning, equalizer adaptation, SNR estimation.
POST /api/photonic-link-train
📉 Photonic BER Bit Error Rate simulation for photonic SerDes links. Extinction ratio, jitter, SNR sweep.
POST /api/photonic-ber
⚙️ Photonic MRM Cal Microring modulator calibration: resonance tuning, thermal stabilization, channel spacing.
POST /api/photonic-mrm-cal
👥 Collaboration & Sharing
🔗 Share Design Generate shareable link with optional expiry. View-only for collaborators.
POST /api/design/{id}/share
🔗 Access Shared Open a shared design by token. Clone to own workspace to edit.
GET /api/share/{share_token}
🔄 Design Diff Compare two snapshots: RTL diff, netlist changes, timing regression.
POST /api/design/{id}/diff/{a}/{b}
📋 Compare Designs Side-by-side comparison: area, power, timing metrics.
POST /api/compare
🌐 Public Designs Browse community reference designs. Clone and learn.
GET /api/designs-public
🌐 Deployment Options
Cloud-Native (Default)
APEX-EDA runs on APEX Cloud. Zero setup. Login and start designing.
Air-Gapped On-Premise
Deploy on your own infrastructure. All data stays within your network. Atavus AI Engine runs locally.
- Docker/Kubernetes deployment
- Offline Atavus AI (7B-229B) via Ollama
- Local DB, file storage, orchestration
- No telemetry, no cloud dependencies
- AES-256-GCM storage, TLS 1.3, HSM support
Start Cloud, Go Air-Gapped
Designs are fully exportable. Start on cloud for convenience, migrate on-premise when ready.
🏢 Startup / Beginner Guide
How a startup or individual engineer can go from idea to manufactured chip using APEX-EDA.
Phase 1: Learn & Prototype (Weeks 1-2)
- Register at apexchipset.com (Startup, $199/mo)
- Write RTL — counter, FIFO, SPI
- Lint + Simulate — verify correctness
- Synthesis — check gate count, area, power
- STA — verify timing closure
Phase 2: Refine & Optimise (Weeks 3-4)
- AI Optimisation — GNN4LS, AI PPA optimiser
- Clock Gating + Retiming — power/frequency
- Multi-Corner STA — PVT verification
- CDC + Formal — verification signoff
- ATPG — test patterns
Phase 3: Physical Design (Weeks 5-6)
- Library Selection — Sky130 (free) or TSMC 28nm
- Floorplan — die size, pad ring, macros
- Place & Route — OpenROAD or AI PnR
- Clock Tree — clock distribution synthesis
- Power Grid — PDN design, IR drop check
Phase 4: Signoff & Tapeout (Weeks 7-8)
- DRC + LVS — foundry rule compliance
- Antenna + ERC + SI — full signoff
- GDS Preview — visual inspection
- X1 Validation — signoff checklist
- Tapeout Submit — manufacturing files
- MPW Shuttle — book fab slot
Cost Comparison
Traditional EDA: $80K-$150K/yr per seat + $50K setup = ~$25K for 8 weeks
APEX-EDA Startup: $199/mo -> $398 for 2 months
Open Source: Free software but 6-10 weeks setup + ~$15K engineer time
APEX-EDA: Production-ready in 5 minutes, AI-guided, support included.
Free PDK: SkyWater 130nm
Open-source and free. Design practical chips (up to ~100K gates) at zero PDK cost. Perfect for startups.
❓ Troubleshooting
Design Issues
- Synthesis fails — Run Lint first. Check for syntax errors, missing semicolons, undeclared wires.
- Timing not closing — Use Critical Paths to find worst path. Reduce logic depth, tighten constraints, enable Retiming + AI Opt.
- DRC violations — Check violation type. Most common: min spacing, density. Use AI DRC Fix for automatic repair.
- Power too high — Enable clock gating, reduce activity factor, use MTCMOS for sleep domains.
Platform Issues
- Design won't load — Refresh. Designs auto-save server-side.
- Results panel blank — Resize panel. Click tool again. Check F12 console.
- Login issues — Reset password. Clear cache. Try incognito.
- Tool timeout — Large designs (>500K gates) take minutes. Check status endpoint.
Common Errors
- Module not found — Top-level module name doesn't match filename.
- Port width mismatch — Wire connected to different-width port. Run Lint.
- Missing clock constraint — Add
create_clock -period 10 [get_ports clk]to SDC. - Density violation — Add fill cells. Set fill density to 50%.
Need Help?
Enterprise plan: direct Slack/Discord support. Startup: check /docs.html.
📎 Appendix
Keyboard Shortcuts
- Enter — Synthesis
- Shift+Enter — Full RTL-to-GDSII flow
- L — Lint
- Ctrl+S — Save
- Ctrl+Z — Undo
- Ctrl+Space — Autocomplete
- Alt+Up/Down — Move line
- Ctrl+/ — Toggle comment
Supported PDKs
- SkyWater 130nm — Open-source, free. 5 metal, 1.8V/3.3V. MPW ~$10K/mm^2.
- GF 180nm — Mixed-signal, low cost.
- TSMC 28nm HPC+ — 9 metal, high-performance.
- TSMC 16nm FinFET — 12 metal, ultra-low power.
- IHP 130nm — SiGe BiCMOS, RF/analogue.
Glossary
- RTL — Register Transfer Level (Verilog/VHDL)
- Synthesis — RTL -> gate-level netlist
- PnR — Place and Route
- CTS — Clock Tree Synthesis
- STA — Static Timing Analysis
- DRC — Design Rule Check
- LVS — Layout vs Schematic
- GDSII — IC layout format for manufacturing
- PDK — Process Design Kit
- MPW — Multi-Project Wafer
- ECO — Engineering Change Order
- ATPG — Automatic Test Pattern Generation
- WNS/TNS — Worst/Total Negative Slack
- MTCMOS — Multi-Threshold CMOS (power gating)
API Reference
Full REST API at apexchipset.com/docs.html. All endpoints return JSON. WebSocket at /ws/design/{id}.