Every endpoint in the APEX-EDA platform, documented with code examples. 74 endpoints across 11 categories.
All API requests require a JWT bearer token obtained from the login endpoint. Tokens expire after 24 hours.
Official client libraries for Python and JavaScript.
Async support, type hints, request batching.
TypeScript-first, ESM + CommonJS.
Marked with NEW = Phase 3 additions.
Returns JWT token valid 24h. Rate limited to 10 req/min.
New account. Verification token sent via email.
Extends JWT by 24h.
Monthly API calls, quota, plan details.
Submit RTL for Yosys+ABC. Verilog/VHDL/SV. Target "asic" or "fpga".
pending/running/completed/failed with ETA.
Verilog or EDIF gate-level netlist.
Area, cell count, estimated frequency.
Qwen3-235B guided optimization. Natural language goals like "reduce area 20%".
Map generic netlist to Liberty library.
Available tech libraries with cell counts.
Upload .lib file for custom mapping.
OpenSTA with SDC. Returns WNS/TNS, critical paths.
All paths sorted by slack. Paginated.
Top N WNS paths with full cell/nets details.
Distribution for visualization.
Full timing report, clock summary, WNS/TNS.
Check consistency, detect conflicts, recommend fixes.
Identify all clock domains, crossings, synchronizers.
Crossing points, sync schemes, metastability analysis.
Improperly synchronized crossings with severity.
Validate dual-FF/FIFO synchronizer against MTBF criteria.
Extract all FSMs from RTL: state encoding, transitions.
Transition graph data for viz.
Unreachable states and transition coverage.
Complete documentation of all FSMs.
KLayout DRC with foundry rule decks.
All violations with type, severity, coordinates.
LVS via KLayout. Match % and discrepancies.
Matched/mismatched nets, shorts, opens.
Available DRC rule decks.
Upload custom .drc/.lvs rule deck.
Dynamic + static power with activity annotation.
Per-cell, per-hierarchy consumption.
Static/dynamic IR drop, voltage map, EM risk.
Auto P/G ring/stripe/mesh generation.
Steady-state/transient thermal simulation.
Aspect ratio, utilization, power domains.
Global + detailed with wirelength minimization.
CTS with target skew/latency/power.
Global + detailed, DRC aware.
Routing congestion heatmap.
Minimal metal fixes.
Upload for preview and verification.
Browser viewer with layer toggle and measurement.
All GDS layers with counts and purpose.
Layout from synthesis/PnR as GDSII.
R/C extraction. Output DSPF/SPEF.
Auto dummy fill for density uniformity.
Complexity, lint score, fanout, depth.
Hierarchical by module, cell type, layer.
Code, toggle, FSM, functional in one pass.
Cyclomatic, hierarchy depth, instantiations.
Crosstalk noise and delay analysis.
PDF/HTML with charts and annotated paths.
Combinational + sequential. Counter-example generation.
Structural/functional diff of two designs.
Configure layer map for any foundry PDK via JSON.
Qwen3-235B optimization from natural language.
AI-driven UVM/SV testbench from specs.
Parameterized AXI4/AXI4-Lite/AXI4-Stream.
Register retiming pre/post reports.
High-fanout detection + buffer tree insertion.
Auto insertion for power reduction.
Optimized I/O with timing closure.
Scan chain, ATPG, fault coverage.
Optimal buffer placement for long wires.
Status, latency, maintenance windows.
Total: 74 endpoints | 11 categories | 25 new in Phase 3 | Updated June 2026