The future of semiconductor design — built in the open.
COMPLETE Q1-Q2 2025
v1.0 — Foundation
Initial platform launch with core EDA capabilities.
- RTL synthesis via Yosys/ABC
- Icarus Verilog simulation
- Web IDE with real-time log streaming
- NL-to-RTL generation
- Design CRUD and file management
- IP library browser
COMPLETE Q3 2025
v2.0 — Advanced Analysis
Added timing analysis, power estimation, and verification tools.
- Static timing analysis (ABC)
- Power estimation (toggle-rate)
- RTL verification with iverilog compile
- Clock domain crossing analysis
- RTL linting via Verilator
- RTL metrics (Halstead, cyclomatic)
COMPLETE Q1-Q2 2026 — v3.0
v3.0 — Professional EDA Suite
Major expansion with 25+ professional endpoints and real algorithms replacing all stubs.
- Force-directed quadratic placement
- A* maze routing with congestion awareness
- Dynamic + leakage power analysis
- DRC / LVS verification
- Clock tree synthesis and analysis
- Clock gating optimization
- Pipeline retiming analysis
- Fanout fix and buffer insertion
- AI-powered optimization engine (GNN4LS, GraphWISE, RL Router)
- FSM extraction from RTL
- Bus interface generation (AXI4/APB)
- Testbench generator
- SDC constraint checker
- IR drop (power grid) analysis (I-GNN)
- Coverage analysis
- GDSII layout preview (SVG)
- PDK mapping (TSMC, SkyWater, GF)
- Design comparison (PPA diff)
- Standard cell library browser
- Netlist export (Verilog/JSON/EDIF)
COMPLETE Q2 2026
v3.5 — Sign-Off Ready PnR
Production-grade place and route — all items shipped.
- Pure Python OpenROAD-class PnR engine (analytic placement, A* maze router, H-tree CTS)
- Multi-corner timing analysis (5 PVT corners)
- Design-for-Test (DFT) scan chain insertion
- Automatic test pattern generation (ATPG) with D-algorithm
- Hierarchical design support (RTL hierarchy viewer)
- Power switch insertion (MTCMOS, 90% leakage reduction)
- Foundry-calibrated standard cell libraries (in progress)
COMPLETE Q2 2026
v4.0 — AI & Ecosystem
AI-powered EDA pipeline and chip design ecosystem.
- 9 AI tools: GNN4LS synthesis, HeteroGNN placement, GraphWISE timing, RL Router, I-GNN IR drop, LayoutTransformer DRC, NSGA-III PPA, Design Memory, Multi-Agent Orchestrator
- APEX X1 chip tape-out (804,800 gates, 8-stage pipeline, 0.79W at 80mm²)
- X1 demo gallery with synthesised Tensor Sparse Core
- Foundry PDK certification pipeline
- IEC 61508 / ISO 26262 safety framework (in progress)
- X2 architecture specification (12nm, 16K PEs, 8,192 TOPS ternary)
- Cross-session design memory (200+ JSONL sync to R6515)
CURRENT Q2-Q3 2026
v5.0 — Cloud Marketplace & Advanced Tools
Full-featured cloud platform with marketplace, tapeout, and advanced generators.
- IP Marketplace (7 seed IPs: RISC-V core, TSC MAC, SOPE Engine, I2C, UART, AES-256, PLL)
- Multi-project wafer (MPW) shuttle management (sky130, GF180, EFabless)
- Direct foundry submission API with DRC/LVS/antenna/timing/DFM/IR-drop checks
- Quantum circuit simulator (Bell states, Shor's algorithm)
- RISC-V processor generator (7-module, 445 lines, RV32I/RV64I, gshare BPU, cache)
- APEX Cloud marketplace for IP trading (public launch)
- Autonomous AI design agents — Natural-language goal → RTL → synthesis → timing pipeline with auto-retry
- Standard Cell Libraries — 444 cells per PDK (sky130, gf180, asap7) with full timing/power/area characterization
- X1 Silicon Validation — 7/7 tests passed: synthesis, timing, DRC, power, I/O, clock tree, area
- SSO + RBAC + Audit — Google/Microsoft/Okta SSO, 4 RBAC roles (admin/designer/viewer/compliance), full audit trail
- Crown Jewel AI — Multi-provider EDA engine (DeepSeek → Grok → Claude → Ollama fallback)
- TSMC/Samsung ecosystem membership
- APEX X1 first silicon
IN PROGRESS Q4 2026 — 2027
v6.0 — Frontier
Next-generation platform with silicon-proven hardware and enterprise certification.
- APEX X2 architecture specification (12nm FinFET, 16 chiplets, 262K PEs, 8192 TOPS)
- X2 performance model — batch inference, sparsity, precision-aware throughput estimation
- X2 power model — PE/SRAM/SerDes/mesh power breakdown with TDP headroom analysis
- X1 first tapeout (v2.3-rc1: 804,800 gates, 74.5mm², 0.725W @ 358MHz in sky130)
- IEC 61508 / ISO 26262 certification
- Full foundry PDK certification (TSMC N5, GF 12LP, Samsung 7nm)
- APEX X2 hardware (12nm FinFET, optical interposer, NV-SRAM, 2027-Q2)